This invention relates to a microprocessor, and particularly to a central processing unit (CPU) for use in a microcomputer having a word data memory.
In prior art microprocessors, in order to improve the access processing to a CPU, the word data memory may be stored with program data arranged in a word order that lower bytes or upper bytes are stored at even number addresses while upper bytes or lower bytes are stored at odd number addresses.
However, when the top lower byte (or the top upper byte) of data is stored in an odd number address, the CPU has to perform addressing twice and to access separately the lower bytes and the upper bytes. The two time memory accessing results in slow process operation.
The object of the present invention provides an improved microprocessor which makes it possible to arrange program data without taking account of memory address.
The further object of the present invention provides an improved microprocessor having word data memories which make high rate processing possible.
A microprocessor having a word data memory according to the present invention includes a CPU data bus, an address register, an incrementer, first and second byte data memories, a data input switching circuit and a data output switching circuit. The CPU data bus has higher bit lines and lower bit lines. The address register stores all the bit information of an address on the CPU data bus in response to an address latching signal. The incrementer receives an address specifying data as well as a logical product of a word/byte specifying signal and the first bit information from the address register, the address specifying data consists of all the remaining bits except the first bit from the address register. The first byte data memory forms a portion of the word data memory to provide a logical addition of the logical product from the incrementer and the address specifying signal. The second byte data memory forms the remaining portion of the word data memory to receive the address specifying output which consists of all the remaining bits except the first bit from the address register. The data input switching circuit selectively transfers into the first and second byte data memories word writing data and byte writing data on the CPU data bus by higher bit units and lower bit units. The data output switching circuit selectively provides data of the first and second byte data memories onto the higher bit lines and the lower bit lines.